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MC10E446, MC100E446 5V ECL 4-Bit Parallel/Serial Converter
Description
The MC10E/100E446 is an integrated 4-bit parallel to serial data converter. The device is designed to operate for NRZ data rates of up to 1.3 Gb/s. The chip generates a divide by 4 and a divide by 8 clock for both 4-bit conversion and a two chip 8-bit conversion function. The conversion sequence was chosen to convert the parallel data into a serial stream from bit D0 to D3. A serial input is provided to cascade two E446 devices for 8 bit conversion applications. Note that the serial output data clocks off of the negative input clock transition. The SYNC input will asynchronously reset the internal clock circuitry. This pin allows the user to reset the internal clock conversion unit and thus select the start of the conversion process. The MODE input is used to select the conversion mode of the device. With the MODE input LOW, or open, the device will function as a 4-bit converter. When the mode input is driven HIGH the internal load clock will change on every eighth clock cycle thus allowing for an 8-bit conversion scheme using two E446's. When cascaded in an 8-bit conversion scheme the devices will not operate at the 1.3 Gb/s data rate of a single device. Refer to the applications section of this data sheet for more information on cascading the E446. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The 100 Series contains temperature compensation.
Features
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PLCC-28 FN SUFFIX CASE 776
MARKING DIAGRAM*
1 28
MCxxxE446FNG AWLYYWW
xxx A WL YY WW G
= 10 or 100 = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
*For additional marking information, refer to Application Note AND8002/D.
* * * * * * * * * *
On Chip Clock /4 and /8 1.5 Gb/s Typical Data Rate Capability Differential Clock and Serial Inputs VBB Output for Single-ended Input Applications Asynchronous Data Synchronization Mode Select to Expand to 8 Bits PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V Internal Input 50 kW Pulldown Resistors ESD Protection: Human Body Model; > 2 kV, Machine Model; > 100 V
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet.
* Meets or Exceeds JEDEC Spec EIA/JESD78 IC * * * *
Latchup Test Flammability Rating: UL 94 V-0 @ 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 525 devices Moisture Sensitivity Level: Pb = 1; Pb-Free = 3 For Additional Information, see Application Note AND8003/D Pb-Free Packages are Available*
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
November, 2006 - Rev. 8
1
Publication Order Number: MC10E446/D
MC10E446, MC100E446
D0 CLK CLK VBB VEE SIN SIN SYNC 26 27 28 1 2 3 4 5 6 7 8 9 10 MC10E446/MC100E446 25 D1 24 D2 23 D3 MODE NC 22 21 20 NC 19 18 17 16 15 14 13 12 11 NC NC VCC SOUT SOUT VCCO NC
Table 1. PIN DESCRIPTION
PIN SIN D0 - D3 SOUT, SOUT CLK, CLK CL/4, CL/4 CL/8, CL/8 MODE SYNC VBB VCC, VCCO VEE NC FUNCTION ECL Differential Serial Data Input ECL Parallel Data Inputs ECL Differential Serial Data Output ECL Differential Clock Inputs ECL Differential /4 Clock Output ECL Differential /8 Clock Output Conversion Mode 4-Bit/8-Bit ECL Conversion Synchronizing Input Reference Voltage Output Positive Supply Negative Supply No Connect
VCCO CL/8 CL/8 VCCO CL/4 CL/4 VCCO * All VCC and VCCO pins are tied together on the die. Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Figure 1. Pinout: PLCC-28 (Top View)
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MC10E446, MC100E446
SIN SIN D3 0 1 CLK VEE 0 D2 1 CLK VEE 0 D1 1 CLK VEE 0 D0 1 CLK VEE LOAD PULSE GENERATOR SOUT SOUT
D
Q
D
Q
D
Q
D
Q
Mode CLK CLK
VEE P4 R VEE
0
1
CL/8 CL/8 P8 R CL/4
Delay
SYNC
CL/4
Figure 2. Logic Diagram
Table 2. FUNCTION TABLES
Mode L H Conversion 4-Bit 8-Bit
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Table 3. MAXIMUM RATINGS
Symbol VCC VI Iout IBB TA Tstg qJA qJC Tsol Parameter PECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm Standard Board PLCC-28 PLCC-28 PLCC-28 Condition 1 VEE = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI v VCC VI w VEE Condition 2 Rating 8 6 -6 50 100 0.5 0 to +85 -65 to +150 63.5 43.5 22 to 26 265 265 Unit V V V mA mA mA C C C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
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Table 4. 10E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 1)
0C Symbol IEE VOH VOHSOUT VOL VIH VIL VBB IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 2) Output HIGH Voltage SOUT/SOUT 3980 3980 3050 3830 3050 3.62 3210 3995 3285 Min Typ 126 4070 Max 151 4160 4210 3370 4160 3520 3.74 150 0.5 0.3 0.5 0.25 4020 4020 3050 3870 3050 3.65 3210 4030 3285 Min 25C Typ 126 4105 Max 151 4190 4240 3370 4190 3520 3.75 150 0.3 0.2 4090 4090 3050 3940 3050 3.69 3227 4110 3302 Min 85C Typ 126 4185 Max 151 4280 4330 3405 4280 3555 3.81 150 Unit mA mV mV mV mV mV V mA mA
Output LOW Voltage (Note 2) Input HIGH Voltage Input LOW Voltage Output Voltage Reference Input HIGH Current Input LOW Current
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. VEE can vary -0.46 V / +0.06 V. 2. Outputs are terminated through a 50 W resistor to VCC - 2.0 V.
Table 5. 10E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = -5.0 V (Note 3)
0C Symbol IEE VOH VOHSOUT VOL VIH VIL VBB IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 4) Output HIGH Voltage SOUT/SOUT -1020 -1020 -1950 -1170 -1950 -1.38 -1790 -1005 -1715 Min Typ 126 -930 Max 151 -840 -790 -1630 -840 -1480 -1.27 150 0.5 0.3 0.5 0.065 -980 -980 -1950 -1130 -1950 -1.35 -1790 -970 -1715 Min 25C Typ 126 -895 Max 151 -810 -760 -1630 -810 -1480 -1.25 150 0.3 0.2 -910 -910 -1950 -1060 -1950 -1.31 -1773 -890 -1698 Min 85C Typ 126 -815 Max 151 -720 -670 -1595 -720 -1445 -1.19 150 Unit mA mV mV mV mV mV V mA mA
Output LOW Voltage (Note 4) Input HIGH Voltage Input LOW Voltage Output Voltage Reference Input HIGH Current Input LOW Current
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. Input and output parameters vary 1:1 with VCC. VEE can vary -0.46 V / +0.06 V. 4. Outputs are terminated through a 50 W resistor to VCC - 2.0 V.
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Table 6. 100E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 5)
0C Symbol IEE VOH VOHSOUT VOL VIH VIL VBB IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 6) Output HIGH Voltage SOUT/SOUT 3975 3975 3190 3835 3190 3.62 3295 3975 3355 Min Typ 126 4050 Max 151 4120 4170 3380 4120 3525 3.73 150 0.5 0.3 0.5 0.25 3975 3975 3190 3835 3190 3.62 3255 3975 3355 Min 25C Typ 126 4050 Max 151 4120 4170 3380 4120 3525 3.74 150 0.5 0.2 3975 3975 3190 3835 3190 3.62 3260 3975 3355 Min 85C Typ 145 4050 Max 174 4120 4170 3380 4120 3525 3.74 150 Unit mA mV mV mV mV mV V mA mA
Output LOW Voltage (Note 6) Input HIGH Voltage Input LOW Voltage Output Voltage Reference Input HIGH Current Input LOW Current
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. VEE can vary -0.46 V / +0.8 V. 6. Outputs are terminated through a 50 W resistor to VCC - 2.0 V.
Table 7. 100E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = -5.0 V (Note 7)
0C Symbol IEE VOH VOHSOUT VOL VIH VIL VBB IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 8) Output HIGH Voltage SOUT/SOUT -1025 -1025 -1810 -1165 -1810 -1.38 -1705 -1025 -1645 Min Typ 126 -950 Max 151 -880 -830 -1620 -880 -1475 -1.27 150 0.5 0.3 0.5 0.25 -1025 -1025 -1810 -1165 -1810 -1.38 -1745 -1025 -1645 Min 25C Typ 126 -950 Max 151 -880 -830 -1620 -880 -1475 -1.26 150 0.5 0.2 -1025 -1025 -1810 -1165 -1810 -1.38 -1740 -1025 -1645 Min 85C Typ 145 -950 Max 174 -880 -830 -1620 -880 -1475 -1.26 150 Unit mA mV mV mV mV mV V mA mA
Output LOW Voltage (Note 8) Input HIGH Voltage Input LOW Voltage Output Voltage Reference Input HIGH Current Input LOW Current
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. Input and output parameters vary 1:1 with VCC. VEE can vary -0.46 V / +0.8 V. 8. Outputs are terminated through a 50 W resistor to VCC - 2.0 V.
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Table 8. AC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = -5.0 V (Note 9)
0C Symbol FMAX tPLH tPHL Characteristic Max Conversion Frequency Propagation Delay to Output CLK to SOUT (Note 10) CLK to CL/4 CLK to CL/8 SYNC to CL/4, CL/8 Setup Time (Note 11) Hold Time (Note 11) Reset Recovery Time Min Pulse Width Random Clock Jitter (RMS) Input Voltage Swing (Differential Configuration) Rise/Fall Times (20% - 80%) Other SOUT 150 100 200 225 425 SIN, Dn SIN, Dn SYNC CLK, MR Min 1.3 Typ 1.6 Max Min 1.3 25C Typ 1.6 Max Min 1.3 85C Typ 1.6 Max Unit Gb/s NRZ 1480 1050 1300 1100 ps
1020 650 800 650 -200 900 500 300
1200 850 1050 850 -450 650 300
1480 1050 1300 1100
1020 650 800 650 -200 900 500 300
1200 850 1050 850 -450 650 300
1480 1050 1300 1100
1020 650 800 650 -200 900 500 300
1200 850 1050 850 -450 650 300
ts th tRR tPW tJITTER VPP tr tf
ps ps ps ps
<1 1000 350 650 150 100 200
<1 1000 225 425 350 650 150 100 200
<1 1000 225 425 350 650
ps mV ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. 10 Series: VEE can vary -0.46 V / +0.06 V. 100 Series: VEE can vary -0.46 V / +0.8 V. 10. Propagation delays measured from negative going clock edge. 11. Relative to negative clock edge. CLK
D
Setup
Valid Data
ts
th
EEEEEEE EEEEEEE EEEEEEE EEEEEEE
Hold
EEEEEEE EEEEEEE EEEEEEE EEEEEEE
SYNC
t rr
CLK
Figure 3.
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CLK RESET D0 D1 D2 D3 SOUT CL/4 CL/8 D0-1 D1-1 D2-1 D3-1 D0-1 D1-1 D2-1 D0-2 D1-2 D2-2 D3-2 D3-1 D0-2 D1-2 D2-2 D3-2
Timing Diagram A. 4:1 Parallel to Serial Conversion
CLK RESET D0 D1 D2 D3 D4 (D0B) D5 (D1B) D6 (D2B) D7 (D3B) SOUT CL/4 CL/8 D0-1 D1-1 D2-1 D3-1 D4-1 D5-1 D6-1 D7-1 D0-1 D1-1 D0-2 D1-2 D2-2 D3-2 D4-2 D5-2 D6-2 D7-2 D2-1 D3-1 D4-1 D5-1 D6-1 D7-1 D0-2
Timing Diagram B. 8:1 Parallel to Serial Conversion Figure 4. Timing Diagrams
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MC10E446, MC100E446
Applications Information The MC10E/100E446 is an integrated 4:1 parallel to serial converter. The chip is designed to work with the E445 device to provide both transmission and receiving of a high speed serial data path. The E446 can convert 4 bits of data into a 1.3 Gb/s NRZ data stream. The device features a SYNC input which allows the user to reset the internal clock circuitry and restart the conversion sequence (see timing diagram A). The E446 features a differential serial input and internal divide by 8 circuitry to facilitate the cascading of two devices to build a 8:1 multiplexer. Figure 1 illustrates the architecture for a 8:1 multiplexer using two E446's; the timing diagram for this configuration can be found on the following page. Notice the serial outputs (SOUT) of the higher order converter feed the serial inputs of the the lower order device. This feed through of the serial inputs bounds the upper end of the frequency of operation. The clock to serial output propagation delay plus the setup time of the serial input pins must fit into a single clock period for the cascade architecture to function properly. Using the worst case values for these two parameters from the data sheet, TPD CLK to SOUT = 1480 ps and tS for SIN = -200 ps, yields a minimum period of 1280 ps or a clock frequency of 780 MHz. The clock frequency is somewhat lower than that of a single converter, to increase this frequency some games can be played with the clock input of the higher order E446. By delaying the clock feeding E446A relative to the clock of E446B the frequency of operation can be increased.
CLK CLK E446B SOUT SOUT Q3 Q2 Q1 Q0 MSB SIN SIN E446A SOUT SOUT Serial Data
Q3 Q2 Q1 Q0 LSB
Q7 Q6 Q5 Q4
Q3 Q2 Q1 Q0
Parallel Data
1000ps 600ps CLOCK Tpd CLK to SOUT 1000ps 1600ps
Figure 5. Cascaded 8:1 Converter Architecture
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Q Driver Device Q Zo = 50 W 50 W 50 W D Zo = 50 W D Receiver Device
VTT VTT = VCC - 2.0 V
Figure 6. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device MC10E446FN MC10E446FNG MC10E446FNR2 MC10E446FNR2G MC100E446FN MC100E446FNG MC100E446FNR2 MC100E446FNR2G Package PLCC-28 PLCC-28 (Pb-Free) PLCC-28 PLCC-28 (Pb-Free) PLCC-28 PLCC-28 (Pb-Free) PLCC-28 PLCC-28 (Pb-Free) Shipping 37 Units / Rail 37 Units / Rail 500 / Tape & Reel 500 / Tape & Reel 37 Units / Rail 37 Units / Rail 500 / Tape & Reel 500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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MC10E446, MC100E446
PACKAGE DIMENSIONS
PLCC-28 FN SUFFIX PLASTIC PLCC PACKAGE CASE 776-02 ISSUE E
Y BRK D Z -L- -M- B 0.007 (0.180) U
M
T L-M
M
S
N
S S
-N-
0.007 (0.180)
T L-M
N
S
W
28 1
D
V
X VIEW D-D
G1
0.010 (0.250)
S
T L-M
S
N
S
A Z R E G G1 0.010 (0.250)
S
0.007 (0.180) 0.007 (0.180)
M M
T L-M T L-M
S S
N N
S S
H
0.007 (0.180)
M
T L-M
S
N
S
C
K1 0.004 (0.100) -T- SEATING
PLANE
J
K F VIEW S 0.007 (0.180)
M
VIEW S T L-M
S
T L-M
S
N
S
N
S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --- 0.025 --- 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 --- 0.020 2_ 10_ 0.410 0.430 0.040 ---
MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --- 0.64 --- 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 --- 0.50 2_ 10_ 10.42 10.92 1.02 ---
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MC10E446, MC100E446
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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MC10E446/D

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